1. Field of the Invention
The present invention relates to a semiconductor memory device and particularly, to a configuration for reducing power consumption of a semiconductor memory device. More particularly, the present invention relates to a configuration for reducing power consumption of an embedded type DRAM (dynamic random access memory) used in a system LSI.
2. Description of the Background Art
In a system LSI constituted of DRAM and a logic such as a processor, ASIC (application specific integrated circuit) or the like in a merged manner, DRAM and the logic are interconnected to each other using an internal data bus of multiple bits such as 128 bits to 512 bits. This internal data bus is on-chip interconnection lines, and a parasitic capacitance and a parasitic resistance thereof are small as compared with those of on-board interconnection lines. Therefore, such a system LSI can achieve a high data transfer speed as compared with a general-purpose high speed DRAM. Furthermore, as compared with a configuration in which a general-purpose DRAM is mounted external to a logic and both are interconnected through on-board interconnection lines, the number of external data input/output pin terminals of the logic can be decreased and a load capacitance of a data bus line between the logic and DRAM can also be reduced by more than one order of magnitude. Therefore, this system LSI can decrease a consumed current greatly. Owing to these advantages, a system LSI has largely contributed to improvement of a performance of information equipment handling a great amount of data such as those in three-dimensional graphic processing, image and speech processing and others.
FIG. 96 is a diagram schematically showing a configuration of a whole of a conventional embedded DRAM used in a system LSI. In FIG. 96, the embedded DRAM includes: a plurality of memory cell arrays MA0 to MAn; sense amplifier bands SB1 to SBn each arranged between the memory cell arrays MA0 to MAn; and sense amplifier bands SB0 and SBn+1 arranged outside the respective memory cell arrays MA0 and MAn. Each of the memory cell arrays MA0 to MAn is divided into a plurality of memory cell sub arrays MSA by sub word driver bands SWDB.
In a memory cell sub array MSA, memory cells are arranged in rows and columns, and sub word lines SWL are provided corresponding to respective rows. A main word line MWL is commonly provided to memory cell sub arrays MSA divided by the sub word driver bands SWDB A in a memory sub array MA. Main word lines MWL are each provided corresponding to a prescribed number of sub word lines in a memory cell sub array MSA.
In a sub word driver band SWDB, sub word drivers are provided corresponding to the sub word lines SWL. Each sub word driver drives a corresponding sub word line to a selected state according to a signal on a corresponding main word line MWL and a sub decode signal, not shown.
In each of the sense amplifier bands SB0 to SBn+1, sense amplifier circuits are provided corresponding to the columns of a corresponding memory cell array. Each sense amplifier circuit of the sense amplifier bands SB1 to SBn is shared between adjacent memory cell arrays. Row decoders each selecting a main word line according to a row address signal are provided corresponding to the respective memory cell arrays MA0 to Man, and column decoders transmitting a column select signal for selecting a column in a memory cell array according to a column address signal onto a column select line CSL are provided in alignment with the row decoders. Column select lines CSL are provided in respective sense amplifier bands and each connect a prescribed number of sense amplifier circuits to a group of internal data bus line pairs GIOP when selected.
The internal data bus line pairs GIOP are arranged extending over the memory arrays MA0-Man in a column direction. A prescribed number of internal data line pairs GIOP are coupled with selected sense amplifier circuits through local data lines LIO. Row decoders and column decoders are arranged in alignment in a row/column decoder band RCDB, and a propagation distance of a column select signal on a column select line CSL is decreased to achieve high speed column selection.
Internal data line pairs GIOP are provided by 128 bits to 512 bits or more and coupled with a data path band DPB including preamplifiers and write drivers. In the data path band DPB, the preamplifiers and the write drivers are provided corresponding to respective global data line pairs GIOP. A global data line pair GIOP may be a data line pair transmitting both of write data and read data, or may include a bus line pair transmitting read data and a write data line pair transmitting write data may be used independently of each other.
The embedded DRAM further includes: a row address circuit/refresh counter RAFK, a column address input circuit CAK receiving an external address A0 to A12 of, for example, 13 bits applied from a logic; a command decoder/control circuit CDC receiving external control signals applied from the logic to generate internal control signals specifying various operations; and a data input/output controller DIOK for performing transfer of data between the data path band DPB and the logic.
The command decoder/control circuit CDC receives a clock signal CLK, a clock enable signal CKE, a row address strobe signal /RAS a column address strobe signal /CAS, a write enable signal /WE and a data mask signal DM, and determines an instructed operating mode according to logical states of the control signals CKE, /RAS, /CAS, /WE and DM at a rising edge of the clock signal CLK. The term “command” indicates a combination of logical states of the plurality of control signals CKE, /RAS, /CAS and /WE at a rising edge of the clock signal CLK. The data mask signal DM instructs write masking, with a byte being a unit, for data applied to the data input/output controller DIOK. The command decoder/control circuit CDC decodes a command applied from the logic to generate an operating mode instructing signal instructing an operating mode specified by the command and furthermore generates various internal control signals for performing the specified operating mode. Commands include: a row active command for setting a row to a selected state; a read command instructing data reading; a write command instructing data writing; a precharge command for placing a selected row in a non-selected state; an auto-refresh command for performing a refresh operation; and a self refresh command for performing self refresh of storage data.
The row address input circuit/refresh counter RAFK takes in external address bits A0 to A12 as a row address under control of the command decoder/control circuit CDC, when a row active command is supplied, to generate an internal row address. The row address input circuit/refresh counter RAFK includes: an address buffer for buffering received address bits; and an address latch for latching an output signal of the buffer circuit. A refresh counter included in the row address input circuit/refresh counter RAFK generates a refresh address specifying a refresh row when an auto-refresh command or a self-refresh command is supplied. A count value of the refresh counter is incremented or decremented each time the refresh operation is completed. The column address input circuit CAK takes in, for example, lower external address bits A0 to A4 to generate an internal column address signal under control of the command decoder/control circuit CDC when a read command or a write command is supplied. The column address input circuit CAK also includes an address buffer and an address latch.
An internal row address signal from the row address input circuit/refresh counter RAFK is applied to a row predecoder RPD, while an internal column address signal from the column address input circuit CAK is applied to a column predecoder CPD. The row predecoder RPD predecodes the received row address signal to apply the predecoded signal to a row decoder included in the row/column decoder band RCDB. The column predecoder CPD predecodes the internal column address from the column address input circuit CAK to apply the predecoded signal to a column decoder included in the row/column decoder band RCDB.
The command decoder/control circuit CDC generates internal control signals for controlling the operations of data input/output controller DIOK and a preamplifier or a write driver included in the data path band DPB. The clock signal CLK is used as a reference signal determining timings of internal operations of the embedded DRAM.
The data input/output controller DIOK performs data inputting/outputting operation in synchronization with the clock signal CLK, and a row address input circuit in the row address input circuit/refresh counter RAFK and the column address input circuit CAK takes in and latch applied address bits in synchronization with the clock signal CLK.
The embedded DRAM further includes: a block PHK including an internal voltage generating circuit for generating internal voltages VPP, VCCS, VCCP, VBL and VCP; and a self-refresh timer activating a refresh request signal FAY at prescribed intervals when a self-refresh mode is specified (a self-refresh command is supplied). The internal voltage VPP is a voltage transmitted onto a selected sub word line SWL, and is normally higher than an operating power supply voltage. The voltage VCCS is an operating power supply voltage of a sense amplifier circuit included in the sense amplifier bands SB0 to SBn+1, and is generated by an internal voltage down converter, not shown. The voltage VCCP is a peripheral power supply voltage or an operating power supply voltage applied to peripheral circuits such as row decoders and column decoders included in the row/column decoder band RCDB, and to preamplifiers and write drivers included in the data path band DPB. The voltage VBL is a bit line precharge voltage described later. The voltage VCP is a cell plate voltage applied to a cell plate of a memory cell, and is at an intermediate level between an H level voltage and an L level voltage of memory cell data. The voltages VBL and VCP each are an intermediate voltage, which is normally at half a level of the array power supply voltage (a sense power supply voltage) VCCS.
A self-refresh timer of the block PHK is activated after entry into the self-refresh mode, to issue refresh request signals at prescribed intervals with a maximum refresh time tREFmax such that refresh of all the rows of the memory cell arrays MA0 to MAn is completed once in the refresh time. When the number of refreshes required for all the rows of the memory arrays MA0 to MAn is represented by Nref, the refresh request signals are issued in a cycle of tREFmax/Nref. For example, in a 4K refresh mode with Nref=4096, the refresh request signal FAY is repeatedly issued every 16 μsec if the maximum refresh time tREFmax is set to 64 ms.
In the self-refresh mode, refresh of memory cell data is performed in a memory cell array at a prescribed period, for holding stored data in memory cells. The self-refresh mode is normally set in a sleep mode, or while the system LSI is in a standby state over a long period. Hence, in the sleep mode, what is required is only to hold storage data of memory cells; and therefore, a refresh interval is preferably set as long as possible from the viewpoint of low power consumption.
FIG. 97 is a diagram representing a configuration of a sense amplifier circuit included in a sense amplifier band and a peripheral section thereof. In FIG. 97, a sense amplifier SAK is coupled with bit lines BLL and ZBLL through a bit line isolation gate BIGL and also coupled with bit lines BLR and ZBLR of another memory block through a bit line isolation gate BIGR. The bit line isolation gates BIGL and BIGR become conductive/non-conductive in response to bit line isolation instructing signals BLIL and BLRR, respectively.
The sense amplifier SAK differentially amplifies a potential on a common bit line CBL coupled with the bit lines BLL and BLR through the bit line isolation gates BIGL and BIGR and a potential on a common bit line ZCBL coupled with the bit lines ZBLL and ZBLR through the bit line isolation gates BIGL and BIGR. The sense amplifier SAK includes: a pair of cross-coupled P channel MOS transistors P1 and P2, and a pair of cross-coupled N channel MOS transistors N1 and N2. There are provided, as a sense amplifier drive circuit, a P channel MOS transistor P3 for sense amplifier activation that is rendered conductive in response to activation of a sense amplifier activating signal ZSOP to transmit the sense power supply voltage VCCS to a sense power supply node S2P of the sense amplifier SAK, and an N channel MOS transistor N3 for sense amplifier activation that is rendered conductive in response to a sense activating signal SON to couple a sense ground node S2N to a ground node. The common bit lines CBL and ZCBL are further coupled with a pair of local data lines LIO through a column select gate CSG. The pair of local data lines LIO is coupled with global data lines GIO and ZGIO.
Furthermore, the bit lines BLL and ZBLL are provided with a bit line precharge/equalize circuit BEQL activated in response to activation of a bit line equalize instructing signal BLEQL, to transmit the bit line precharge voltage VBL onto the bit lines BLL and ZBLL. The bit lines BLR and ZBLR are provided with a bit line precharge/equalize circuit BEQR activated in response to activation of a bit line equalize instructing signal BLEQR, to transmit the bit line precharge voltage VBL onto the bit lines BLR and ZBLR.
Sub word lines are provided crossing the bit lines BLL and ZBLL, and the bit lines BLR and ZBLR, and memory cells MC are placed corresponding to the crossings. In FIG. 88, a sub word line SWL crossing the bit lines BLL and ZBLL and a memory cell MC placed at a location corresponding to a crossing between the sub word line SWL and the bit line ZBLL are representatively shown. A memory cell MC includes: a memory capacitor MQ for storing information; and an access transistor MT constituted of an N channel MOS transistor and made conductive in response to a potential of the sub word line, to couple the memory capacitor MQ with the bit line ZBLL. A potential on a storage node SN of the memory capacitor MQ is determined according to the stored information, while a cell plate arranged facing to the storage node is supplied with the cell plate voltage VCP.
In the standby state, the bit line isolation instructing signals BLIL and BLIR are at H level of, for example, the boosted voltage VPP level. Thus, the bit line isolation gates BIGL and BIGR are in a conductive state, and the bit lines BLL, CBL and BLR are coupled with each other, and the complementary bit lines ZBLL, ZCBL and ZBLR are coupled with each other. In this state, the bit line equalize instructing signal BLEQL and BLEQR are also in an active state, and the bit lines BLL, CBL and BLR and the complementary bit lines ZBLL, ZCBL and ZBLR are precharged and equalized at the precharge voltage VBL by the bit line precharge/equalize circuits BEQL and BEQR.
When a row active command is applied and a row access is to be made, a bit line isolation gate of a memory cell block including a selected row (sub word line) stays in a conductive state, while a bit line isolation gate for a non-selected memory cell array sharing a sense amplifier with the selected memory cell array (the memory cell array including the selected sub word line) enters a non-conductive state. Now, consider a case where the sub word line shown in FIG. 97 is selected. In this case, the bit line equalize signal BLEQL is in an inactive state at L level, and the bit line precharge/equalize circuit BEQL is deactivated. Furthermore, the bit line isolation instructing signal BLIR is driven to L level, the bit line isolation gate BIGR enters a non-conductive state and the bit lines BLR and ZBLR are disconnected from the common bit lines CBL and ZCBL. In this state, the bit lines BLL and ZBLL of a selected memory cell array enter a floating state at the precharge voltage VBL. The bit line equalize instructing signal BLEQR is in an active state at H level, and the bit lines BLR and ZBLR are held at the bit line precharge voltage VBL level by the bit line precharge/equalize circuit BEQR.
Then, a row select operation is performed and a potential of a selected sub word line rises. When a level of the sub word line SWL rises, the memory access transistor MT of a memory cell MC is made conductive to couple the storage node SN of the memory capacitor MQ with a corresponding bit line (ZBLL). Accordingly, an electric charge accumulated in the capacitor MQ of the memory cell is read onto the associated bit line ZBLL. Since the selected memory cell is not connected to the bit line BLL, the bit line BLL is held at the bit line precharge voltage VBL of the intermediate level. Now, when parasitic capacitance values of the bit lines BLL and ZBLL are represented by CB, a capacitance value of the memory capacitor MQ by CS and a potential on the storage node SN by V(SN), a potential difference ΔV between the bit lines BLL and ZBLL is expressed by the following formula:ΔV=0.5·V(SN)·CS/(CS+CB).
Then, the sense amplifier activating signals ZSP and SON are activated, the MOS transistors P3 and N3 for sense amplifier activation are made conductive, and the sense power supply voltage VCCS and the sense ground voltage are transmitted to sense power source nodes S2P and S2N. When the sense power supply voltage VCCS and the sense ground voltage are transmitted to the sense power source nodes S2P and S2N, the sense amplifier SAK is activated to start a sense operation. Generally, since threshold voltages of the N channel MOS transistors N1 and N2 are smaller in absolute value than threshold voltages of the P channel MOS transistors P1 and P2, an N sense amplifier constituted of the MOS transistors N1 and N2 starts a sense operation first to amplify a potential difference transmitted from the bit lines BLL and ZBLL to the common bit lines CBL and ZCBL. That is, a common bit line of a lower potential level of the common bit lines CBL and ZCBL is driven to the ground voltage level by the MOS transistors N1 and N2. A little later, another common bit line of a higher potential level of the common bit lines CBL and ZCBL is driven to the sense power supply voltage VCCS by the P channel MOS transistors P1 and P2.
When L level data is transmitted onto the common bit lines CBL and ZCBL, a voltage on a common bit line receiving the data of L level is lower than the precharge voltage VBL. On the other hand, when H level data is read out, a voltage of a common bit line receiving the data of H level is higher than the precharge voltage VBL. Hence, since a gate to source voltage of the MOS transistors N1 and N2 is lower when data of L level is read out as compared to the case where data of H level is read out, a sense operation of the N channel MOS transistors N1 and N2 is slower when the data of L level is read out as compared to the case where the data of H level is read out.
A magnitude of the voltage that the sense amplifier SAK senses is proportional to the voltage V(SN) on the storage node SN of the memory cell MC. Hence, in order to increase a sense margin to operate the sense amplifier SAK correctly, it is needed to increase an amount of electric charges read out from the memory cell as much as possible. A potential level on the storage node SN when data of L level is stored is the ground voltage VSS level, and a voltage V(SN) on the storage node SN is the sense power supply voltage VCCS level when data of H level is stored. In order to raise a voltage level on the storage node SN to the possible maximum when data of H level is stored, the boosted voltage VPP is transmitted onto the sub word line SWL. The boosted voltage VPP is a voltage sufficiently higher than the sum of the sense power supply voltage VCCS and a threshold voltage of the access transistor MT. By transmitting the boosted voltage VPP onto the sub word line SWL, the sense power supply voltage VCCS can be transmitted onto the storage node SN without a loss due to the threshold voltage of the memory access transistor MT.
When the sense operation by the sense amplifier SAK is completed, the bit lines BLL and ZBLL are driven to the sense power supply voltage VCCS and the ground voltage level. Thereafter, a read command or a write command (a column access command) is supplied, a column select operation is performed, and a column select signal on the column select line CSL is activated. Responsively, the column select gate CSG for the selected column is made conductive, and the common bit lines CBL and ZCBL are coupled with the global data lines GIO and ZGIO through the local lines LIO, and data writing or reading is performed.
FIG. 98 is a diagram schematically showing a cross sectional structure of a memory cell. In FIG. 98, N type impurity regions 901a and 901b are formed spaced from each other on a surface of a P type substrate region 900. A first conductive layer 902 serving as a word line is formed above a channel region between the impurity regions 901a and 901b with a gate insulating film, not shown, interposed therebetween. The impurity region 901a is connected to a second conductive layer 903 serving as a bit line, while the impurity region 901b is connected to a third conductive layer 904 serving as a storage node SN. The third conductive layer 904 has a leg region connected to the impurity region 901b and a hollow cylindrical region on the leg region. A fourth conductive layer 906 serving as a cell plate electrode is formed on the cylindrical region with a capacitor insulating film 905 interposed therebetween. The fourth conductive layer 906 serving as the cell plate extends across a corresponding to memory cell sub array with a memory cell sub array being a unit, and memory cells in the corresponding memory sub array on the cell plate commonly receive the cell plate voltage VCP at the cell plate nodes. The cylindrical region in an upper portion of the third conductive layer 904 and an facing region of the fourth conductive layer 906 through the capacitor insulating film 905 function as a memory capacitor.
The memory access transistor MT is constructed of the impurity regions 901a and 901b, and the first conductive layer 902. The substrate region 900 functions as a back gate of the memory access transistor MT and receives a negative voltage Vbb. A potential of the third layer 904 is determined according to stored data. However, as shown with a broken line in FIG. 98, electric charge accumulated in the memory capacitor decreases by various leakage currents such as a leakage current through a junction capacitance of the storage node SN (a capacitance of a PN junction between the impurity region 901b and the substrate region 900), a leakage current in a channel region beneath the second conductive layer 902 and a leakage current through the capacitor insulating film 905 and others.
FIG. 99 is a graph representing a change over time in the potential level of the storage node SN. FIG. 99 shows a change in the voltage V(SN) when the precharge voltage VBL (=VCCS/2) is applied on the bit line BL and the ground voltage VSS is applied on the word like WL (the sub word line SWL). The voltage V(SN) on the storage node SN has a time dependency expressed by the following formula due to leakage current:V(SN)≈Vbb+(VCCS−Vbb)·exp(−T/τa), where T indicates a time and a coefficient τa is an electric charge holding characteristic value of a memory cell storing data of H level. As the characteristic value τa is larger, an electric charge holding time of a memory cell is longer.
When data of H level has been written onto the storage node SN, a voltage V(SN) of the storage node SN is at a level of the sense power supply voltage VCCS. The storage node voltage V(SN) gradually decreases with time T due to a leakage current through a PN junction. If a memory cell data is read out onto the bit line when the storage node attains a voltage Vcr at time T1, a potential difference between bit lines, at that time, (Vcr−VBL)·Cs/(Cs+Cb) is lower than a sensitivity of the sense amplifier, where Cs and Cb indicate respective capacitance values of the memory cell capacitor and a bit line parasitic capacitance. That is, after the time T1 elapses, the sense amplifier malfunctions, read error for H data arises in which H level data may be amplified into L level data. Hence, refresh need be performed on this memory cell within a time of T1 to rewrite or restore the data. The characteristic value τa of each memory cell is different from others (due to variation in fabrication parameters), and therefore, a refresh time is determined taking the worst case into consideration. That is, the maximal refresh time tREFmax is determined based on the memory cell with the shortest data holding time, in other words, based on the smallest characteristic value τa available.
In a fabrication process for an embedded DRAM, the same process as that for a logic integrated on the same chip is employed. Therefore, in order to obtain full performances of transistors in the logic, a salicidation process or the like applied on source and drain diffusion layers of a transistor, which has been a standard step in a process for the logic, has been introduced into the process for an embedded DRAM. Hence, a thermal budget (a product of time and temperature in an annealing process) in a high temperature processing applied in formation of the memory capacitor is reduced. For this reason, an impurity region and an insulating film cannot be subject to a thermal process at a prescribed temperature for a sufficient time, resulting in an increased junction leakage current and in an increased leakage current through a capacitor insulating film, although by a small amount.
Furthermore, in a case where a stacked capacitor cell structure of a cylindrical shape is adopted as shown in FIG. 98, a high step is caused between a DRAM section and a logic section. Such a step cannot be perfectly eliminated even when an interlayer insulating film between interconnection lines is planarized to some extent by a CMP (a chemical mechanical polishing) process. Accordingly, a pitch of metal interconnection lines cannot be reduced sufficiently because of irregular reflection and others at steps in an exposure process of a photolithographic process. Hence, a metal interconnection line pitch required for a high density library of a logic is difficult to be achieved. Therefore, with a capacitance value of a memory capacitor sacrificed to some extent, a height of a storage node is decreased (a height of a cylindrical section is decreased) to achieve a complete planarization of an interlayer insulating film between interconnection lines, to eliminate a step between the DRAM section and the logic section for increasing a gate density of a logic library. Therefore, a capacitance value of a memory capacitor is smaller than in a general purpose DRAM and thus, an amount of accumulated electric charges is accordingly reduced.
Furthermore, an embedded DRAM is integrated together with a logic section operating at high speed on the same semiconductor chip. Therefore, temperature of the embedded DRAM section tends to be higher as compared with that of a general purpose DRAM due to heat conduction from the logic. In addition, a power supply line of the embedded DRAM section and the substrate are apt to be affected by noise due to a high speed operation of the logic section. Refresh characteristics of the embedded DRAM are deteriorated as compared with a general purpose DRAM by these various factors in the fabrication process or a chip operation. Moreover, during operation, a refresh time of an embedded DRAM is required to be short as compared with a general purpose DRAM, thereby increasing a current consumed for data holding.
Furthermore, in a case where a logic section ceases its operation as in the sleep mode or the like, a self-refresh is required to be periodically performed in order to hold stored data in the embedded DRAM. In this case as well, a refresh time in the self-refresh mode becomes short as compared with a general purpose DRAM. Therefore, a consumed current in the sleep mode increases. Especially, in a case where a system LSI with an embedded DRAM is applied in products such as a portable information equipment and digital camera driven by a battery, a power consumption is a more predominant factor than increase in storage capacity. Accordingly, increase in consumed current associated with poor refresh characteristics is a serious problem against application to a battery driven equipment.